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x86_64: all intermediate page table entries now have PTE_USR set

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this allows user-accessible page mappings to be created. for kernel memory
mappings, PTE_USR will only be cleared on the lowest-level table entry.
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max 🍓
2026-02-08 13:03:41 +00:00
parent 67b3be9732
commit 5f2ad06fb0
1 changed files with 1 additions and 1 deletions
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arch/x86_64/pmap.c
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@@ -15,7 +15,7 @@
#define C_2GiB (2 * C_1GiB) #define C_2GiB (2 * C_1GiB)
#define BAD_INDEX ((unsigned int)-1) #define BAD_INDEX ((unsigned int)-1)
#define PTR_TO_ENTRY(x) (((x) & ~VM_PAGE_MASK) | PTE_PRESENT | PTE_RW) #define PTR_TO_ENTRY(x) (((x) & ~VM_PAGE_MASK) | PTE_PRESENT | PTE_RW | PTE_USR)
#define ENTRY_TO_PTR(x) ((x) & ~VM_PAGE_MASK) #define ENTRY_TO_PTR(x) ((x) & ~VM_PAGE_MASK)
#define PFN(x) ((x) >> VM_PAGE_SHIFT) #define PFN(x) ((x) >> VM_PAGE_SHIFT)