From 5f2ad06fb0246fe7d8bc0bc7e30bf49f874c22a4 Mon Sep 17 00:00:00 2001 From: Max Wash Date: Sun, 8 Feb 2026 13:03:41 +0000 Subject: [PATCH] x86_64: all intermediate page table entries now have PTE_USR set this allows user-accessible page mappings to be created. for kernel memory mappings, PTE_USR will only be cleared on the lowest-level table entry. --- arch/x86_64/pmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86_64/pmap.c b/arch/x86_64/pmap.c index 0ed104e..96ff69b 100644 --- a/arch/x86_64/pmap.c +++ b/arch/x86_64/pmap.c @@ -15,7 +15,7 @@ #define C_2GiB (2 * C_1GiB) #define BAD_INDEX ((unsigned int)-1) -#define PTR_TO_ENTRY(x) (((x) & ~VM_PAGE_MASK) | PTE_PRESENT | PTE_RW) +#define PTR_TO_ENTRY(x) (((x) & ~VM_PAGE_MASK) | PTE_PRESENT | PTE_RW | PTE_USR) #define ENTRY_TO_PTR(x) ((x) & ~VM_PAGE_MASK) #define PFN(x) ((x) >> VM_PAGE_SHIFT)