acpi: add APIC irq ack and legacy vector remapping

arch/x86_64/acpi/apic.cpp

@@ -1,6 +1,8 @@
 #include <socks/printk.h>
 #include <socks/vm.h>
 #include <socks/cpu.h>
+#include <arch/acpi/io_apic.hpp>
+#include <arch/acpi/local_apic.hpp>
 #include <arch/acpi.h>
 #include <arch/msr.h>
 #include <arch/ports.h>
@@ -13,7 +15,12 @@
 #define IA32_APIC_BASE_MSR_BSP 0x100
 #define IA32_APIC_BASE_MSR_ENABLE 0x800
 
+static int apic_enabled = 0;
+
+using namespace arch::acpi;
+
 static uint32_t *lapic_base;
+static queue_t io_apics;
 
 extern "C" {
 	/* defined in apic_ctrl.S */
@@ -37,16 +44,6 @@ static void disable_8259(void)
 	outportb(PIC2_DATA, 0xFF);
 }
 
-static uint32_t local_apic_read(uint32_t reg)
-{
-	return READ_ONCE(lapic_base[reg >> 4]);
-}
-
-static void local_apic_write(uint32_t reg, uint32_t val)
-{
-
-}
-
 static void *find_lapic(struct acpi_madt *madt)
 {
 	phys_addr_t local_apic = madt->m_lapic_ptr;
@@ -82,27 +79,93 @@ kern_status_t local_apic_enable(void)
 
 	apic_set_base(apic_get_base());
 	lapic_base = (uint32_t *)find_lapic(madt);
+	local_apic lapic(lapic_base);
 
-	local_apic_write(0xF0, local_apic_read(0xF0) | 0x100);
+	lapic.write(0xF0, 0x1FF);
+	lapic.ack();
 
 	printk("acpi: enabled local APIC on core %u", this_cpu());
 	return KERN_OK;
 }
 
+static io_apic *get_ioapic_for_irq(unsigned int vec)
+{
+	queue_foreach (io_apic, ioapic, &io_apics, io_entry) {
+		if (vec >= ioapic->io_first_irq && vec < ioapic->io_first_irq + ioapic->io_nr_irq) {
+			return ioapic;
+		}
+	}
+
+	return nullptr;
+}
+
 static void configure_legacy_pic(void)
 {
 	printk("acpi: APIC unavailable, using 8259 PIC");
-	pit_start(1000);
+	pit_start(10);
 }
 
-static void ioapic_init(void)
+static void ioapic_init(uintptr_t base, unsigned int int_base)
 {
+	uint32_t *base_vaddr = (uint32_t *)vm_phys_to_virt(base);
+	io_apic *apic = kmalloc_object(io_apic, VM_NORMAL, base_vaddr, int_base);
 
+	printk("acpi: I/O APIC at 0x%llx; base=%u, irqs=%u", base, int_base, apic->io_nr_irq);
+
+	for (unsigned int i = 0; i < apic->io_nr_irq; i++) {
+		apic->map_irq(i, 32 + int_base + i);
+	}
+
+	queue_push_back(&io_apics, &apic->io_entry);
 }
 
-static void init_all_ioapic(void)
+static void parse_legacy_irq_override(struct acpi_madt *madt)
 {
-	ioapic_init();
+	unsigned char *p = (unsigned char *)madt + sizeof *madt;
+	unsigned char *madt_end = (unsigned char *)madt + madt->m_base.s_length;
+
+	while (p < madt_end) {
+		struct acpi_madt_record *rec = (struct acpi_madt_record *)p;
+		struct acpi_madt_irqsrc_override*irq;
+		io_apic *handler = nullptr;
+
+		switch (rec->r_type) {
+		case ACPI_MADT_IRQSRC_OVERRIDE:
+			irq = (struct acpi_madt_irqsrc_override *)(rec + 1);
+			printk("acpi: irq src=%u, dest=%u", irq->irq_srcvec, irq->irq_destvec);
+			handler = get_ioapic_for_irq(irq->irq_srcvec);
+			handler->map_irq(irq->irq_srcvec, 32 + irq->irq_destvec);
+			break;
+		default:
+			break;
+		}
+
+		p += rec->r_length;
+	}
+}
+
+static void init_all_ioapic(struct acpi_madt *madt)
+{
+	unsigned char *p = (unsigned char *)madt + sizeof *madt;
+	unsigned char *madt_end = (unsigned char *)madt + madt->m_base.s_length;
+
+	while (p < madt_end) {
+		struct acpi_madt_record *rec = (struct acpi_madt_record *)p;
+		struct acpi_madt_ioapic *ioapic;
+
+		switch (rec->r_type) {
+		case ACPI_MADT_IOAPIC:
+			ioapic = (struct  acpi_madt_ioapic *)(rec + 1);
+			ioapic_init(ioapic->io_address, ioapic->io_intbase);
+			break;
+		default:
+			break;
+		}
+
+		p += rec->r_length;
+	}
+
+	parse_legacy_irq_override(madt);
 }
 
 kern_status_t apic_init(void)
@@ -123,12 +186,30 @@ kern_status_t apic_init(void)
 	}
 
 	if (this_cpu() == bsp_id) {
-		init_all_ioapic();
+		init_all_ioapic(madt);
 	}
 
 	local_apic_enable();
         disable_8259();
 
+	apic_enabled = 1;
+
 	pit_start(10);
+	printk("acpi: all APIC online");
 	return KERN_OK;
 }
+
+void irq_ack(unsigned int vec)
+{
+	if (apic_enabled) {
+		local_apic lapic(lapic_base);
+		lapic.ack();
+	} else {
+		if (vec >= 40) {
+			outportb(0xA0, 0x20);
+		}
+
+		outportb(0x20, 0x20);
+	}
+
+}

arch/x86_64/acpi/io_apic.cpp

@@ -0,0 +1,65 @@
+#include <socks/compiler.h>
+#include <socks/printk.h>
+#include <arch/acpi/io_apic.hpp>
+
+#define IOAPICID        0x00
+#define IOAPICVER       0x01
+#define IOAPICARB       0x02
+#define IOAPICREDTBL(n) (0x10 + 2 * n)
+
+namespace arch::acpi {
+	io_apic::io_apic(uint32_t *base, unsigned int first_irq) : io_base(base), io_first_irq(first_irq)
+	{
+		io_nr_irq = ((read(IOAPICVER) >> 16) + 1) & 0xFF;
+	}
+
+	uint32_t io_apic::read(uint32_t reg)
+	{
+		*(volatile uint32_t *)(io_base) = reg & 0xFF;
+		return *(volatile uint32_t *)((char *)io_base + 0x10);
+	}
+
+	void io_apic::write(uint32_t reg, uint32_t val)
+	{
+		*(volatile uint32_t *)(io_base) = reg & 0xFF;
+		*(volatile uint32_t *)((char *)io_base + 0x10) = val;
+	}
+
+	kern_status_t io_apic::read_irq(unsigned int index, irq_entry &entry)
+	{
+		if (index >= io_nr_irq) {
+			return KERN_NO_ENTRY;
+		}
+
+		uint32_t *entry_data = (uint32_t *)&entry;
+		entry_data[0] = read(IOAPICREDTBL(index));
+		entry_data[1] = read(IOAPICREDTBL(index) + 1);
+
+		return KERN_OK;
+	}
+
+	void io_apic::write_irq(unsigned int index, const irq_entry &entry)
+	{
+		if (index >= io_nr_irq) {
+			return;
+		}
+
+		const uint32_t *entry_data = (const uint32_t *)&entry;
+		write(IOAPICREDTBL(index), entry_data[0]);
+		write(IOAPICREDTBL(index) + 1, entry_data[1]);
+	}
+
+	void io_apic::map_irq(unsigned int src, unsigned int dest)
+	{
+		io_apic::irq_entry irq{};
+		irq.irq_vec = dest;
+		irq.irq_delivery = 0;
+		irq.irq_destmode = 0;
+		irq.irq_polarity = 0;
+		irq.irq_triggermode = 0;
+		irq.irq_mask = 0;
+		irq.irq_dest = 0;
+
+		write_irq(src, irq);
+	}
+}

arch/x86_64/acpi/local_apic.cpp

@@ -0,0 +1,25 @@
+#include <arch/acpi/local_apic.hpp>
+#include <socks/vm.h>
+
+#define LAPIC_REG_EOI 0xB0
+
+namespace arch::acpi {
+	local_apic::local_apic(uint32_t *base) : base_(base)
+	{
+	}
+
+	uint32_t local_apic::read(uint32_t reg)
+	{
+		return *(volatile uint32_t *)((char *)base_ + reg);
+	}
+
+	void local_apic::write(uint32_t reg, uint32_t val)
+	{
+		*(volatile uint32_t *)((char *)base_ + reg) = val;
+	}
+
+	void local_apic::ack()
+	{
+		*(volatile uint32_t *)((char *)base_ + LAPIC_REG_EOI) = 0;
+	}
+}

arch/x86_64/include/arch/acpi.h

@@ -11,6 +11,7 @@ extern "C" {
 
 #define ACPI_MADT_LAPIC  0x00
 #define ACPI_MADT_IOAPIC 0x01
+#define ACPI_MADT_IRQSRC_OVERRIDE 0x02
 #define ACPI_MADT_LAPIC_OVERRIDE 0x05
 
 #define ACPI_SIG_RSDP 0x2052545020445352ULL
@@ -79,6 +80,22 @@ struct acpi_madt_record {
 	uint8_t r_length;
 } __packed;
 
+struct acpi_madt_ioapic {
+	uint8_t io_apic_id;
+	uint8_t io_reserved;
+	uint32_t io_address;
+	uint32_t io_intbase;
+} __packed;
+
+struct acpi_madt_irqsrc_override {
+	uint8_t irq_bus;
+	/* the irq vector as delivered from the APIC to the CPU */
+	uint8_t irq_destvec;
+	/* the irq vector as delivered from the hardware to the APIC */
+	uint32_t irq_srcvec;
+	uint16_t irq_flags;
+} __packed;
+
 struct lapic_record {
 	uint8_t l_cpu_id;
 	uint8_t l_apic_id;
@@ -99,6 +116,8 @@ extern kern_status_t smp_init(void);
 
 extern struct acpi_sdt *acpi_find_sdt(uint32_t sig);
 
+extern void irq_ack(unsigned int vec);
+
 #ifdef __cplusplus
 }
 #endif

arch/x86_64/include/arch/acpi/io_apic.hpp

@@ -0,0 +1,39 @@
+#ifndef ARCH_ACPI_IOAPIC_HPP_
+#define ARCH_ACPI_IOAPIC_HPP_
+
+#include <stdint.h>
+#include <socks/status.h>
+#include <socks/queue.h>
+
+namespace arch::acpi {
+	struct io_apic {
+		uint32_t *io_base = nullptr;
+		unsigned int io_first_irq = 0;
+		unsigned int io_nr_irq = 0;
+		queue_entry_t io_entry;
+
+		struct irq_entry {
+			uint64_t irq_vec : 8;
+			uint64_t irq_delivery : 3;
+			uint64_t irq_destmode : 1;
+			uint64_t irq_status : 1;
+			uint64_t irq_polarity : 1;
+			uint64_t irq_irr : 1;
+			uint64_t irq_triggermode : 1;
+			uint64_t irq_mask : 1;
+			uint64_t irq_resv : 39;
+			uint64_t irq_dest : 8;
+		};
+
+		io_apic(uint32_t *base, unsigned int first_irq);
+
+		uint32_t read(uint32_t reg);
+		void write(uint32_t reg, uint32_t val);
+
+		kern_status_t read_irq(unsigned int index, irq_entry &entry);
+		void write_irq(unsigned int index, const irq_entry &entry);
+		void map_irq(unsigned int src, unsigned int dest);
+	};
+}
+
+#endif

arch/x86_64/include/arch/acpi/local_apic.hpp

@@ -0,0 +1,19 @@
+#ifndef ARCH_ACPI_LOCAL_APIC_HPP_
+#define ARCH_ACPI_LOCAL_APIC_HPP_
+
+#include <stdint.h>
+
+namespace arch::acpi {
+	class local_apic {
+		uint32_t *base_ = nullptr;
+
+	public:
+		local_apic(uint32_t *base);
+
+		uint32_t read(uint32_t reg);
+		void write(uint32_t reg, uint32_t val);
+		void ack();
+	};
+}
+
+#endif

arch/x86_64/include/socks/machine/cpu.h

@@ -20,8 +20,11 @@ typedef struct ml_cpu_block {
 	unsigned int c_cpu_id;
 } ml_cpu_block;
 
-#define ml_cpu_pause() asm volatile("hlt")
+#define ml_cpu_pause() __asm__ __volatile__("hlt")
-#define ml_cpu_relax() asm volatile("pause")
+#define ml_cpu_relax() __asm__ __volatile__("pause")
+
+#define ml_int_disable() __asm__ __volatile__("cli")
+#define ml_int_enable() __asm__ __volatile__("sti")
 
 extern int ml_init_bootcpu(void);
 

arch/x86_64/init.c

@@ -75,7 +75,7 @@ int ml_init(uintptr_t arg)
 
 	acpi_init();
 
-	asm volatile("sti");
+	ml_int_enable();
 
 	return 0;
 }

arch/x86_64/irq.c

@@ -1,5 +1,6 @@
 #include <arch/irq.h>
 #include <arch/ports.h>
+#include <arch/acpi.h>
 #include <socks/printk.h>
 #include <socks/libc/string.h>
 #include <socks/machine/irq.h>
@@ -217,7 +218,7 @@ int idt_init(struct idt_ptr *ptr)
 
 int idt_load(struct idt_ptr *ptr)
 {
-	asm volatile("lidt (%0)" ::"r" (ptr));
+	__asm__ __volatile__("lidt (%0)" ::"r" (ptr));
 	return 0;
 }
 
@@ -231,16 +232,11 @@ void isr_dispatch(struct cpu_context *regs)
 
 void irq_dispatch(struct cpu_context *regs)
 {
-    if (regs->int_no >= 40) {
+	irq_ack(regs->int_no);
-	    outportb(0xA0, 0x20);
+	queue_t *hooks = &irq_hooks[regs->int_no - IRQ0];
-    }
+	queue_foreach(irq_hook_t, hook, hooks, irq_entry) {
-
+		hook->irq_callback();
-    outportb(0x20, 0x20);
+	}
-
-    queue_t *hooks = &irq_hooks[regs->int_no - IRQ0];
-    queue_foreach(irq_hook_t, hook, hooks, irq_entry) {
-	    hook->irq_callback();
-    }
 }
 
 void syscall_dispatch(struct cpu_context *regs)
@@ -248,16 +244,6 @@ void syscall_dispatch(struct cpu_context *regs)
 
 }
 
-void ml_int_enable()
-{
-	asm volatile("sti");
-}
-
-void ml_int_disable()
-{
-	asm volatile("cli");
-}
-
 void hook_irq(irq_vector_t vec, irq_hook_t *hook)
 {
 	queue_t *hook_queue = &irq_hooks[vec - IRQ0];

arch/x86_64/pmap.c

@@ -272,7 +272,7 @@ void pmap_bootstrap(void)
 	}
 
 	pmap_switch(kernel_pmap);
-	printk("pmap: kernel pmap initialised");
+	printk("pmap: kernel pmap initialised (0x%llx)", kernel_pmap);
 }
 
 pmap_t pmap_create(void)

arch/x86_64/ports.c

@@ -2,38 +2,38 @@
 
 uint8_t inportb(uint16_t port) {
     uint8_t data;
-    asm volatile("inb %1, %0" : "=a"(data) : "dN"(port));
+    __asm__ __volatile__("inb %1, %0" : "=a"(data) : "dN"(port));
     return data;
 }
 
 void outportb(uint16_t port, uint8_t data) {
-    asm volatile("outb %1, %0" : : "dN"(port), "a"(data));
+    __asm__ __volatile__("outb %1, %0" : : "dN"(port), "a"(data));
 }
 
 uint16_t inportw(uint16_t port) {
     uint16_t data;
-    asm volatile("inw %1, %0" : "=a"(data) : "dN"(port));
+    __asm__ __volatile__("inw %1, %0" : "=a"(data) : "dN"(port));
     return data;
 }
 
 void outportw(uint16_t port, uint16_t data) {
-    asm volatile("outw %1, %0" : : "dN"(port), "a"(data));
+    __asm__ __volatile__("outw %1, %0" : : "dN"(port), "a"(data));
 }
 
 uint32_t inportl(uint16_t port) {
     uint32_t data;
-    asm volatile("inl %%dx, %%eax" : "=a"(data) : "dN"(port));
+    __asm__ __volatile__("inl %%dx, %%eax" : "=a"(data) : "dN"(port));
     return data;
 }
 
 void outportl(uint16_t port, uint32_t data) {
-    asm volatile("outl %%eax, %%dx" : : "dN"(port), "a"(data));
+    __asm__ __volatile__("outl %%eax, %%dx" : : "dN"(port), "a"(data));
 }
 
 void outportsw(uint16_t port, void *data, uint32_t size) {
-    asm volatile("rep outsw" : "+S"(data), "+c"(size) : "d"(port));
+    __asm__ __volatile__("rep outsw" : "+S"(data), "+c"(size) : "d"(port));
 }
 
 void inportsw(uint16_t port, unsigned char *data, unsigned long size) {
-    asm volatile("rep insw" : "+D"(data), "+c"(size) : "d"(port) : "memory");
+    __asm__ __volatile__("rep insw" : "+D"(data), "+c"(size) : "d"(port) : "memory");
 }