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asm: implement instruction decoding

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This commit is contained in:
max 🍓
2025-05-12 15:49:53 +01:00
parent c1ba6e78bc
commit fe23529c6b
2 changed files with 81 additions and 6 deletions
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18
asm/include/ivy/asm/instr.h
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@@ -1,8 +1,11 @@
#ifndef IVY_ASM_INSTR_H_
#define IVY_ASM_INSTR_H_
#include <blue/core/endian.h>
#include <ivy/misc.h>
#include <ivy/opcode.h>
#include <ivy/status.h>
#include <stdint.h>
#define R_MASK_OP 0x01800C03u
#define R_MASK_R1 0x000003FCu
@@ -17,11 +20,18 @@
(((i) & ~R_MASK_OP) | (op & 0x03u) | ((op & 0x0Cu) << 8) \
| ((op & 0x30u) << 19))
#define R_GET_OPCODE(i) \
(((i) & 0x03u) | (((i) >> 8) & 0x0Cu) | (((i) >> 19) & 0x30u))
#define R_SET_R1(i, r) (((i) & ~R_MASK_R1) | ((r & 0xFFu) << 2))
#define R_SET_R2(i, r) (((i) & ~R_MASK_R2) | ((r & 0xFFu) << 12))
#define R_SET_R3(i, r) \
(((i) & ~R_MASK_R3) | ((r & 0x01u) << 22) | ((r & 0xFEu) << 24))
#define R_GET_R1(i) (((i) >> 2) & 0xFFu)
#define R_GET_R2(i) (((i) >> 12) & 0xFFu)
#define R_GET_R3(i) (((i) >> 22) & 0x01u) | (((i) >> 24) & 0xFEu)
#define R_SET_D1(i, r) \
(((i) & ~R_MASK_D1) | ((r & 0x07u) << 20) | ((r & 0x3F8u) << 22))
#define R_SET_D2(i, r) \
@@ -30,6 +40,12 @@
(((i) & ~R_MASK_D3) | ((r & 0xFFu) << 2) | ((r & 0x7FF00u) << 4) \
| ((r & 0x3F80000u) << 6))
#define R_GET_D1(i) ((((i) >> 20) & 0x07u) | (((i) >> 22) & 0x3F8u))
#define R_GET_D2(i) ((((i) >> 12) & 0x7FFu) | (((i) >> 14) & 0x3F800u))
#define R_GET_D3(i) \
((((i) >> 2) & 0xFFu) | (((i) >> 4) & 0x7FF00u) \
| (((i) >> 6) & 0x3F80000u))
enum ivy_instr_layout {
IVY_INSTR_X = 0,
IVY_INSTR_D,
@@ -69,4 +85,6 @@ struct ivy_instr {
IVY_API const struct ivy_instr_definition *ivy_instr_find(
enum ivy_instr_id id, const enum ivy_instr_operand_type operands[4]);
IVY_API enum ivy_status ivy_instr_decode(b_i32 instr, struct ivy_instr *out);
#endif